1. Field of the Invention
The present invention relates to a thin film transistor array substrate and a manufacturing method of the same, and more particularly to the thin film transistor array substrate and the manufacturing method of the same capable of reducing the number of mask processes.
2. Discussion of the Related Art
In general, a liquid crystal display represents an image by means of adjusting a transmissivity of light of the liquid crystal by use of an electric field. For this purpose, the liquid crystal display comprises a liquid crystal display panel where the liquid crystal cells are arranged by a matrix type, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel comprises a thin film transistor array substrate and a color filter array substrate facing each other, a spacer located for maintaining a designated cell gap between two substrates, and the liquid crystal filling to the cell gap.
The thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed as a switching device at every intersection of the gate lines and the data lines, a pixel electrode connected to the thin film transistor formed by the liquid crystal cell unit, and an alignment film spread thereon. The gate lines and the data lines receive signals from driving circuits through each of the pad part. The thin film transistor responds to a scan signal supplied to the gate line, and supplies to the pixel electrode a pixel voltage signal supplied to the data line.
The color filter array substrate includes the color filters formed by the liquid crystal cell unit, a black matrix for reflecting outside light and separating between the color filters, a common electrode commonly supplying a reference voltage to the liquid crystal cells, and an alignment film spread thereon.
The liquid crystal display panel combines a specially manufactured thin film transistor array substrate and color filter array substrate, in which liquid crystal is injected there between, after which the panel is sealed. With respect to this liquid crystal panel, the thin film transistor array substrate includes a semiconductor process and in addition includes a plurality of mask processes. Accordingly, the manufacturing process is complicated and this is the main cause of the rising costs of manufacturing the liquid crystal display panel. In order to solve this problem, the thin film transistor array substrate is improved in order to reduce the number of mask processes. The reason for this is that in one mask process, many sub-processes such as an evaporation process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process are all included in one mask process. Recently, 4-mask process have appeared, replacing more conventional 5-mask process.
FIG. 1 is a plane view illustrating the thin film transistor array substrate adopting a mask process, and FIG. 2 is a sectional view illustrating as cutting along line I–I′ the thin film transistor array substrate as shown in FIG. 1.
The thin film transistor array substrate as shown in FIG. 1 and FIG. 2 comprises gate lines 2 and data lines 4 formed as intersecting each other and putting a gate insulation film there between on a lower substrate 42, a thin film transistor 6 formed at every intersection, and a pixel electrode 18 formed in the cell region arranged by the intersection. And the thin film transistor array substrate comprises a storage capacitor 20 formed at a superimposed part of the pixel electrode 18 and the former gate line 2, a gate pad part 26 connected to the gate line 2, and a data pad part 34 connected to the data line 4.
The thin film transistor 6 comprises a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 16, an active layer 14 forming a channel between the source electrode 10 and the drain electrode 12 superimposed with the gate electrode 8. The active layer 14 is formed as being superimposed with the data pad 36, the storage electrode 22, the data line 4, the source electrode 10, and the drain electrode 12, and further comprises the channel part between the source electrode 10 and the drain electrode 12. On the active layer 14, the data pad 36, the storage electrode 22, the data line 4, the source electrode 10, the drain electrode 12, and an ohmic contact layer 48 for ohmic contact are further formed. This thin film transistor 6 responds to the gate signal supplied to the gate line 2 and provides a pixel voltage signal supplied to the data line 4 at the pixel electrode 18.
The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through a first contact hole 16 penetrating a protection film 50. The pixel electrode 18 generates a voltage difference from the common electrode formed on the upper substrate (not shown) when a pixel voltage is provided. By this voltage difference, the liquid crystal located between the thin film transistor substrate and the upper substrate rotates due to a dielectric anisotropy, and allows incident light passing through the pixel electrode 18 from the light source (not shown) to be emitted to the upper substrate.
The storage capacitor 20 comprises a former stage gate line 2, a storage electrode superimposed over the gate line 2, the gate insulation film 44, the active layer 14, the ohmic contact layer 48 there between, and the pixel electrode 22 connected through the second contact hole 24 formed at the protection film 50. In addition the capacitor 20 superimposes the storage electrode 22 over the protection film 50. This storage capacitor 20 makes the pixel voltage supplied to the pixel electrode 18 constant until the next pixel voltage is supplied thereto.
The gate line 2 is connected to the gate driver (not shown) through the gate pad part 26. The gate pad part 26 comprises the gate pad 28 extended from the gate line 2 and the gate pad protection electrode 32 connected to the gate pad 28 through the third contact hole 30 penetrating the gate insulation film 44 and the protection film 50.
The data line 4 is connected to the data driver (not shown) through the data pad part 34. The data pad part 34 comprises the data pad 36 extended from the data line 4 and the data pad protection electrode 40 connected to the data pad 36 through the fourth contact hole 38 penetrating the protection film 50.
The thin film transistor array substrate having this constitution is fabricated by a 4-mask process.
FIG. 3a and FIG. 3d are sectional views illustrating the method of manufacturing the thin film transistor array substrate.
Referring to FIG. 3a, the gate patterns are formed on the lower substrate 42.
On the lower substrate 42, the gate metal layer is formed by an evaporation method such as a sputtering method. Subsequently, the gate metal layer is patterned by the photolithography process using the first mask and the etching process thereby forming the gate patterns including a gate line 2, a gate electrode 8, and a gate pad 28. As a gate metal, chrome (Cr), molybdenum (Mo), aluminum (Al), or the like can be used for the single layer or the double layer structure.
Referring to FIG. 3b, on the lower substrate 42 where the gate patterns are formed, a gate insulation film 44, an active layer 14, an ohmic contact layer 48, and a source/drain patterns are subsequently formed also.
On the lower substrate 42 where the gate pattern is formed by the evaporation method such as a PECVD, a sputtering, or the like, a gate insulation film 44, an amorphous silicon layer, a n+ amorphous silicon layer, and the source/drain metal layer are subsequently formed.
On the source/drain metal layer, a photoresist pattern is formed by a photolithography process using the second mask. In this case, for the second mask, a diffraction exposure mask having the diffraction exposure part in the channel part of the thin film transistor is used. The photoresist pattern of the channel part has a height lower than the other source/drain pattern part.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photoresist pattern, and the source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12 combined as one body with the source electrode 10, and the storage electrode 22 are formed.
Then, the n+ amorphous silicon layer and the amorphous silicon layer are at the same time patterned by a dry etching process using the same photoresist pattern, and thus the ohmic contact layer 48 and the active layer 14 are formed.
In the channel part after the photoresist pattern having a low relative height is removed by the ashing process, the source/drain pattern of the channel part and the ohmic contact layer 48 are etched by the dry etching process. In this way, the active layer 14 of the channel part is exposed and the source electrode 10 and the drain electrode 12 are separated.
Subsequently, the photoresist pattern existing on the source/drain pattern part is removed by the strip process.
As a material for the gate insulation film 44, an inorganic insulation material like as a silicon oxide (SiOx) or a silicon nitride (SiNx) is used. As a source/drain metal, a molybdenum (Mo), a titanium (Ti), a tantalum (Ta), molybdenum alloy, or the like are used.
Referring to FIG. 3c, on the gate insulation film 44 where the source/drain patterns are formed, the protection film 50 including the first to the fourth contact holes 16, 24, 30, 38 are formed.
On the gate insulation film 44 where the source/drain patterns are formed, the protection film 50 is wholly formed by the evaporation method like as PECVD. The protection film 50 is patterned by the photolithography process and the etching process using the third mask, forming the first to the fourth contact holes (16, 24, 30, 38. The first contact hole 16 penetrates the protection film 50 and is formed so that the drain electrode 12 is exposed. The second contact hole 24 penetrates the protection film 50 and is formed so that the storage electrode 22 is exposed. The third contact hole 30 penetrates the protection film 50 and the gate insulation film 44 and is formed so that the gate pad 28 is exposed. The fourth contact hole 38 penetrates the protection layer 50 and is formed so that the data pad 6 is exposed.
As a material for the protection film 50, an inorganic insulation material like that used as the gate insulation film 94 or an organic insulation material such as an acryl organic compound, BCB, and PFCB having a dielectric coefficient that is low is used.
Referring to FIG. 3d, the transparent electrode patterns are formed on the protection film 50.
On the protection film 50, the transparent electrode material is wholly evaporated by the evaporation method such as the sputtering. Subsequently, the transparent electrode material is patterned by the photolithography process and the etching process using the fourth mask, forming the transparent electrode pattern including the pixel electrode 18, the gate pad protection electrode 32, and the data pad protection electrode 4. The pixel electrode 18 is electrically connected to the drain electrode 12 through the first contact hole 16 and is electrically connected to the storage electrode superimposed with a former stage gate line 2 through the second contact hole 24. The gate pad protection electrode 32 is electrically connected to the gate pad 28 through the third contact hole 30. The data pad protection electrode 40 is electrically connected to the data pad 36 through the fourth contact hole 38. As the transparent electrode material, Indium Tin Oxide (ITO), Tin Oxide (TO), or Indium Zinc Oxide (IZO) is used. The related art thin film transistor substrate and the manufacturing method such as this reduce the number of manufacture processes by adopting a 4-mask process in contrast with the 5-mask process previously used. In addition, this can decrease the manufacturing cost proportionally. But, because the manufacturing process of the 4-mask process is still complicated, the potential cost reduction is limited. It is required that the thin film transistor substrate and the manufacture method thereof further reduce the manufacturing cost by further simplifying the manufacturing process.